Design Verification Engineer
- Expired: over a month ago. Applications are no longer accepted.
Title: 100% Remote-Quick Interview-Design Verification Engineer
Location: CA; San Jose
• Testbench development - System Verilog UVM and C tests
• Integration/development of C tests/APIs and SW build flow
• Integration/development of UVM mailboxes and HW/SW communication components
• Test plan development
• Power Aware testbench development and simulations
• Seamless porting between simulation/emulation/prototyping platforms
• Regression setup and debug for RTL/Gate Level Netlist/UPF PA sim/Emulation/Proto
• Coverage collection and closure
• Working with cross functional teams (DV/Arch/Design/FW) to identify coverage scope
• Engage with the team to drive continuous improvement to the verification environment to find more bugs and improve coverage
• Work as a team to grow together.
• Mentor and coach junior team members
• A minimum of three years of experience with SoC Design Verification
• Bachelor’s Degree or equivalent (12 years) work experience (If an, Associate’s Degree with 6 years of work experience)
• Experience with PCIe Verification
• Experience with ARM Cortex
• In-depth knowledge of digital logic design, chip architecture and microarchitecture
• Experience in developing TestPlan/testbenches, SystemVerilog/UVM/C-based TestBench, and writing/debugging tests
• Experience with advanced verification techniques such as different booting verification, end-to-end verification; multiple CPUs verification as part of the IP is desirable.
• Experience in ARM AMBA protocols; AXI4, AHB and APB.
• Team player with excellent communication skills and be able to work independently on the verification efforts for a block/area of the design
TechnologyView all jobs at Pyramid Consulting
Get fresh Senior Design Verification Engineer jobs daily straight to your inbox!
You Already Have an Account
We're sending an email you can use to verify and access your account.
If you know your password, you can go to the sign in page.