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ASIC Engineer

Crossbar Inc. Santa Clara, CA
  • Posted: over a month ago
  • Full-Time
  • Benefits: Vision, Medical, Life Insurance, 401k, Dental

Job Description

· Participate in Architecture and Microarchitecture specifications

· Verilog RTL development and debug, publish and maintain design spec and micro-architecture spec

· Hands on experience in all aspects of chip development process with proficiency in front end tools and methodologies

· Experience or knowledge of system architecture, CPU & IP Integration, and power and clock management designs desirable.

· Work closely with verification team for test plan/strategy to meet all functional requirements and performance, defining verification strategy and reviewing test plan

· Familiarity with scripting languages like Python is a plus

· Familiarity with FPGA is a plus

· Familiarity with software and operating concepts is a plus

· Ability to communicate effectively across all internal groups

· Work closely with timing and physical team for timing closure and meet power and area goals

Qualifications

· BS/MS in Electronics Engineering with minimum of 5 years of ASIC frontend & behavioral modeling experiences

· Strong in communication, leadership, investigation, problem solving & analytical skill

· Proficiency with Verilog RTL coding (LEC, CDC, DFT)

· Well verse in interface timing budget & clock domain crossing design

· Familiar with SoC designs and micro-Architecture

· Familiar with scripting language like Python

Crossbar Inc.

Crossbar Inc. is a dynamic start-up company focused on delivering solutions that will dramatically enhance the global memory storage industry. Backed by top tier investors, we have assembled an expert team of leading financial, marketing, legal and engineering professionals. We are committed to our vision of transforming the content storage and delivery mechanism for the entire memory industry. Visit us at www.crossbar-inc.com

Address

Santa Clara, CA
USA

Website

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