Currently seeking an FPGA Verification Engineer to join our Team in Atlanta.
*Able to design new or make improvements to verification test benches and test cases
· Designing with all aspects of Universal Verification Methodology (UVM) based verification methodologies
· Creating a detailed verification plan
· Applying coverage extraction, creation and implementation when needed
· Collaborative and good communications skills
· Excellent debugging and problem solving skills
· Capable of working independently on the assigned design activities with minimal supervision
· Work effectively with internal designers and external contractors
- Self-starting, Highly Self Motivating
· Travel 0-10%
- Other duties as required
Customers (Internal & External)
· FPGA/IP Development Manager
· Project Managers for Projects
· HW/SW Team Personnel
Skills / Qualifications / Training / Experience:
· Bachelor of Science Degree in computer engineering or electrical engineering.
· 2-5 years of experience verifying complex Application Specific Integrated Circuits/Field Programmable Gate Arrays (ASICs / FPGAs).
· 2-5 years of experience in ASIC / FPGA verification using C/C++ and/or System Verilog.
· 2-5 years of experience with verification methodology UVM
· 2-5 years of experience with building and setting up scalable simulation / verification environments.
· 2-5 years of experience with scripting (bash/csh, Perl, TCL, Python, etc.).
· Tools: Mentor Questa Synopsys DVE
· Linux Operating System
PHYSICAL DEMANDS AND WORKING ENVIRONMENT
- Ability to remain stationary for long periods of time;
· Able to work at a desk majority of the day
· Moderate lifting, 15-44 lbs
- Ability to use a computer keyboard and computer screen for extensive computer work (preparing documents spreadsheets and communications via electronic mail)
- Ability to regularly work a minimum of 40 hours per week
PREFERRED SKILLS AND EXPERIENCE:
· Master’s Degree in Computer Engineering, Electrical Engineering or equivalent.
· Constrained Random Verification experience, highly desired.
· Any FPGA/ASIC design experience is a definite plus.
· Experience with any network protocols (OTN, Ethernet, FC, SONET)
· Familiarity with testing complex designs, code coverage, functional coverage, assertions.
· Ability to focus on finding design issues, corner cases and out of box ideas to make designs more robust.
· Demonstrate the ability to work in a dynamic environment that includes working with changing needs and requirements.
- Develop leadership abilities – help others with technical issues
- Design abilities- develop Models and Test bench components
- Languages – Verilog, VHDL, python, linux OS scripting, web based, metadata related languages (html,html5,java)
- Methodology – ASIC Design/Verification Flow
- Tools – Mentor Questa/ModelSim, Synopsys VCS, Quartus, Vivado, ISE, SVN, Formal Tools, Clock Domain Analysis, Code Coverage
- G.709 Digital Wrapper Standard, GBE, Fibre Channel
- Microprocessor Interfaces
- PCI Variants