What You Can Expect - Define and scales RTL development, drive reuse across IP and programs - Owns ... A Director of Silicon Design for PCIe and Memory must combine deep protocol expertise, good ...
What You Can Expect - Define and scales RTL development, drive reuse across IP and programs - Owns ... A Director of Silicon Design for PCIe and Memory must combine deep protocol expertise, good ...
What You Can Expect - Define and scales RTL development, drive reuse across IP and programs - Owns ... A Director of Silicon Design for PCIe and Memory must combine deep protocol expertise, good ...
What You Can Expect - Define and scales RTL development, drive reuse across IP and programs - Owns ... A Director of Silicon Design for PCIe and Memory must combine deep protocol expertise, good ...
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... You are an experienced RTL design engineer with strong communication skills. You have a passion for ...
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... You are an experienced RTL design engineer with strong communication skills. You have a passion for ...
As a Design Verification Engineer, you will work closely with our RTL development engineers, system ... directed, and system-level testbenches • Develop and maintain stimulus generators, drivers ...
As a Design Verification Engineer, you will work closely with our RTL development engineers, system ... directed, and system-level testbenches • Develop and maintain stimulus generators, drivers ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
ASIC/RTL Design Engineer Primary Skills : RTL coding, TCL coding, Python coding, understanding of different CAD tools (synthesis, lint, CDC, RDC, PrimeTime). Location: San Jose CA Duration : 12 ...
CPU MicroArchitect / RTL Engineer - Site Lead
Beaverton, OR · On-site
$106K - $140K/yr
... design principles along with timing and power implications Previous experience leading a team of senior engineers to deliver complex microarchitecture definition and RTL development, including direct ...
CPU MicroArchitect / RTL Engineer - Site Lead
Beaverton, OR · On-site
$106K - $140K/yr
... design principles along with timing and power implications Previous experience leading a team of senior engineers to deliver complex microarchitecture definition and RTL development, including direct ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · Hybrid
$132K - $181K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · Hybrid
$132K - $181K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
Director Silicon Design Engineering
Santa Clara, CA · On-site
$217K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... THE ROLE: AMD is looking for an experienced technical leader to drive RTL design for future ...
Director Silicon Design Engineering
Santa Clara, CA · On-site
$217K/yr
... direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the ... THE ROLE: AMD is looking for an experienced technical leader to drive RTL design for future ...
CPU MicroArchitect / RTL Engineer - Site Lead
$106K - $140K/yr
... refinement of RTL design to target power, performance, area and timing goals • Validation ... direct individual technical contribution Record of mentoring and supporting the career development ...
CPU MicroArchitect / RTL Engineer - Site Lead
$106K - $140K/yr
... refinement of RTL design to target power, performance, area and timing goals • Validation ... direct individual technical contribution Record of mentoring and supporting the career development ...
Design Verification Engineer - Remote
$139K - $169K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Drive constrained random and directed testing strategies to validate functionality, corner cases ...
Design Verification Engineer - Remote
$139K - $169K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Drive constrained random and directed testing strategies to validate functionality, corner cases ...
FPGA Design Engineer
Los Angeles, CA · Hybrid
$132K - $182K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
FPGA Design Engineer
Los Angeles, CA · Hybrid
$132K - $182K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of FPGA Engineering on the FPGA Engineering team. The successful individual in this role will ...
$170K - $250K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...
Director, ASIC Design
$210K - $240K/yr
About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions ... Proficiency in Verilog/SystemVerilog RTL design. * Knowledge of synthesis and static timing ...
Director, ASIC Design
$210K - $240K/yr
About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions ... Proficiency in Verilog/SystemVerilog RTL design. * Knowledge of synthesis and static timing ...
Design Verification Engineer/Analyst
San Jose, CA · On-site
$159K - $194K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...
Quick apply
Design Verification Engineer/Analyst
San Jose, CA · On-site
$159K - $194K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...
Director, ASIC Design
San Jose, CA · On-site
About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions ... Proficiency in Verilog/SystemVerilog RTL design. * Knowledge of synthesis and static timing ...
Quick apply
Director, ASIC Design
San Jose, CA · On-site
About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions ... Proficiency in Verilog/SystemVerilog RTL design. * Knowledge of synthesis and static timing ...
Director, ASIC Design
San Jose, CA · On-site
$210K - $240K/yr
About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions ... Proficiency in Verilog/SystemVerilog RTL design. * Knowledge of synthesis and static timing ...
Director, ASIC Design
San Jose, CA · On-site
$210K - $240K/yr
About the Role As a Director, ASIC Design you will lead the development of advanced ASIC solutions ... Proficiency in Verilog/SystemVerilog RTL design. * Knowledge of synthesis and static timing ...
Senior Engineer, GPU RTL Power
Austin, TX · On-site
$109K - $146K/yr
Understanding of physical design and STA flows and their interaction with power optimization ... direct impact on consumer technologies used worldwide. Here you'll help build what's next ...
Senior Engineer, GPU RTL Power
Austin, TX · On-site
$109K - $146K/yr
Understanding of physical design and STA flows and their interaction with power optimization ... direct impact on consumer technologies used worldwide. Here you'll help build what's next ...
Design and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation ... Criminal history may have a direct, adverse, and negative relationship with some of the material ...
Design and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation ... Criminal history may have a direct, adverse, and negative relationship with some of the material ...
OR · On-site
$130K - $200K/yr
... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ... Drive constrained-random and directed testing strategies to validate functionality, corner cases ...
Design Verification Engineer - Viasat Government
Marlborough, MA · On-site
$164K - $246K/yr
Experience in RTL design and development and FPGA implementation is a plus, and the ideal candidate ... directed, and system-level testbenches * Develop and maintain stimulus generators, drivers ...
Design Verification Engineer - Viasat Government
Marlborough, MA · On-site
$164K - $246K/yr
Experience in RTL design and development and FPGA implementation is a plus, and the ideal candidate ... directed, and system-level testbenches * Develop and maintain stimulus generators, drivers ...
Director Rtl Design information
See salary details
$37K - $55.7K
8% of jobs
$55.7K - $74.5K
0% of jobs
$74.5K - $93.2K
7% of jobs
$108.1K is the 25th percentile. Wages below this are outliers.
$93.2K - $111.9K
12% of jobs
The median wage is $129.4K / yr.
$111.9K - $130.6K
24% of jobs
$130.6K - $149.4K
16% of jobs
$159.1K is the 75th percentile. Wages above this are outliers.
$149.4K - $168.1K
15% of jobs
$168.1K - $186.8K
11% of jobs
$186.8K - $205.5K
7% of jobs
$205.5K - $224.3K
0% of jobs
$224.3K - $243K
0% of jobs
$37K
$135.8K
$243K
How much do director rtl design jobs pay per year?

Other
Life, Retirement
Posted 18 days ago
Job description
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
The Center of Excellence (COE), part of the Custom Compute and Storage (CCS) Business Unit within Marvell's Data Center Group, is chartered to define, develop, and maintain standard, production-ready IP subsystems - spanning PCIe/CXL, Ethernet, DDR/Memory, Security/Boot, Low-Speed IO, and other critical technologies - that customers and internal SoC teams can adopt with confidence. By shifting left, the COE enables faster time-to-market, reduces integration risk, and ensures compliance, interoperability, and high performance across Marvell's SoC products. It embodies the "One Marvell" principle - sharing reusable components, verification environments, and knowledge across all business units to drive first-pass-right silicon. As part of the COE, you will design, verify, and deliver IP subsystem building blocks powering Marvell's most advanced custom chips for hyperscale cloud, AI, and data center customers - working at the intersection of architecture, RTL design, verification, firmware/software, and silicon validation.What You Can Expect
- Define and scales RTL development, drive reuse across IP and programs
- Owns delivery of end-to-end PCIE/CXL and Memory subsystem RTL design execution and sign off
- Collaborates with architecture, DV, firmware, SOC and post-silicon teams to influence specifications early and reduce downstream risk.
- Manages distributed RTL Design teams, develops technical depth and future leaders.
- Accountable for Design schedules, risk assessment, physical design closure, and transparent communication of tapeout readiness to senior management and key stakeholders
- Review and resolve cross-program technical issues and escalations
- Engage with ecosystem partners (JEDEC, IP vendors, PHY providers) on interoperability and enablement
What We're Looking For
The Custom Cloud Solutions Group (CCS) is looking for a Silicon Design Technical Director with a demonstrated track record of success in launching products with specific expertise in PCIe and Memory technologies. The person will be responsible for high-quality, predictable delivery of scalable PCIE and Memory subsystems as part of the center of excellence (COE) to all CCS SOC products in 2027 and beyond. A Director of Silicon Design for PCIe and Memory must combine deep protocol expertise, good understanding of silicon design and computer architecture, knowledge of physical design, experience in power and performance optimization and strong people management to ensure A0 silicon production for complex SoCs. Requirements include:
- BS/MS/PhD in Computer Science, Electrical Engineering, or Computer Engineering with 10-15 years of relevant professional experience.
- Proven experience delivering complex PCIE/CXL and/or Memory subsystems from architecture through RTL closure
- Strong experience in System Verilog RTL development, physical design convergence, power and performance optimization and silicon bring up.
- Experience with EDA verification and debugging tools, scripting languages such as Python or Perl, and revision control systems.
- Effective communication and teamwork skills
- Mindset for high quality and attention to detail
- Independent learner, proactive in problem-solving and finding creative solutions
- a good understanding of PCIE/CXL architectures and memory technologies (DDR, LPDDR, HBM).
- Proven track record of owning complex subsystems end-to-end across multiple products.
- Proven track record of leading distributed, diverse teams across sites.
Expected Base Pay Range (USD)
185,390 - 277,700, $ per annumThe successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
#LI-JT2About Marvell
Sourced by ZipRecruiter
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1995