$100K - $500K/yr
... synthesis, and power analysis. * Proficient in debugging RTL/logic across multiple design ... CPU. * Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and ...
$100K - $500K/yr
... synthesis, and power analysis. * Proficient in debugging RTL/logic across multiple design ... CPU. * Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and ...
As a CPU Physical Design Engineer, you will work with microarchitecture and RTL design team to ... Experience with Synthesis, place and route and signoff timing/power analysis. * Knowledge of high ...
As a CPU Physical Design Engineer, you will work with microarchitecture and RTL design team to ... Experience with Synthesis, place and route and signoff timing/power analysis. * Knowledge of high ...
Senior CPU Physical Design Engineer
Austin, TX · On-site
$134K - $138K/yr
Execute all aspects of the CPU physical design flow, including synthesis, floor planning, place and ... Bachelor's degree in Computer Engineering or Electrical Engineering similar discipline with 5+ ...
Senior CPU Physical Design Engineer
Austin, TX · On-site
$134K - $138K/yr
Execute all aspects of the CPU physical design flow, including synthesis, floor planning, place and ... Bachelor's degree in Computer Engineering or Electrical Engineering similar discipline with 5+ ...
Senior CPU Physical Design Engineer
$134K - $138K/yr
Execute all aspects of the CPU physical design flow, including synthesis, floor planning, place and ... Bachelor's degree in Computer Engineering or Electrical Engineering similar discipline with 5+ ...
Senior CPU Physical Design Engineer
$134K - $138K/yr
Execute all aspects of the CPU physical design flow, including synthesis, floor planning, place and ... Bachelor's degree in Computer Engineering or Electrical Engineering similar discipline with 5+ ...
CPU Design Timing Engineer
Austin, TX · On-site
As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
CPU Design Timing Engineer
Austin, TX · On-site
As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
Description As a CPU Design Timing Engineer, you will be responsible for the timing closure of the ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
Description As a CPU Design Timing Engineer, you will be responsible for the timing closure of the ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
CPU Design Timing Engineer
Austin, TX · On-site
As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
CPU Design Timing Engineer
Austin, TX · On-site
As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
Description As a CPU Design Timing Engineer, you will be responsible for the timing closure of the ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
Description As a CPU Design Timing Engineer, you will be responsible for the timing closure of the ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
Engineering Group, Engineering Group > CPU Engineering General Summary: As a leading technology ... synthesis place and/or route and design verification. • 6+ years of work experience with ...
Engineering Group, Engineering Group > CPU Engineering General Summary: As a leading technology ... synthesis place and/or route and design verification. • 6+ years of work experience with ...
Physical Design Engineer
San Jose, CA · On-site
$159K - $164K/yr
Title: Physical Design Engineer Location: 100% Remote Duration: Long Term Contract role ... Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low ...
Physical Design Engineer
San Jose, CA · On-site
$159K - $164K/yr
Title: Physical Design Engineer Location: 100% Remote Duration: Long Term Contract role ... Experience in running physical-aware logic synthesis and achieving optimal synthesis QoR on low ...
Description As a CPU Design Timing Engineer, you will be responsible for the timing closure of the ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
Description As a CPU Design Timing Engineer, you will be responsible for the timing closure of the ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project ... synthesis, PnR, parasitic extraction, and logic equivalence Understanding of deep sub-micron ...
As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project ... synthesis, PnR, parasitic extraction, and logic equivalence Understanding of deep sub-micron ...
CPU Design Timing Engineer
Austin, TX · On-site
As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
CPU Design Timing Engineer
Austin, TX · On-site
As a CPU Design Timing Engineer, you will be responsible for the timing closure of the project ... aware synthesis and place & route tools and flows, extraction, and other analysis flows, and ...
As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project ... synthesis, PnR, parasitic extraction, and logic equivalence Understanding of deep sub-micron ...
As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project ... synthesis, PnR, parasitic extraction, and logic equivalence Understanding of deep sub-micron ...
M icro-architecture and design of RISC based CPU. * E xplore latest technologies in processor for 5G application. Minimum Qualifications: * M aster Degree in Electrical Engineering, Computer Science ...
M icro-architecture and design of RISC based CPU. * E xplore latest technologies in processor for 5G application. Minimum Qualifications: * M aster Degree in Electrical Engineering, Computer Science ...
CPU Digital Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Micro-architecture and design of RISC based CPU. * Explore latest technologies in processor for 5G application. Minimum Qualifications: * Master Degree in Electrical Engineering, Computer Science or ...
CPU Digital Design Engineer
Sunnyvale, CA · On-site
$159K/yr
Micro-architecture and design of RISC based CPU. * Explore latest technologies in processor for 5G application. Minimum Qualifications: * Master Degree in Electrical Engineering, Computer Science or ...
Sr. Engineer, CPU RTL Design
Austin, TX · On-site
$100K - $500K/yr
... synthesis, and power analysis. * Proficient in debugging RTL/logic across multiple design ... CPU. * Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and ...
Sr. Engineer, CPU RTL Design
Austin, TX · On-site
$100K - $500K/yr
... synthesis, and power analysis. * Proficient in debugging RTL/logic across multiple design ... CPU. * Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and ...
Engineering Group, Engineering Group > CPU Engineering General Summary: As a leading technology ... synthesis place and/or route and design verification. • 2+ years of work experience with ...
Engineering Group, Engineering Group > CPU Engineering General Summary: As a leading technology ... synthesis place and/or route and design verification. • 2+ years of work experience with ...
CPU Design Timing Engineer
$147K - $272K/yr
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... synthesis, PnR, parasitic extraction, and logic equivalence Understanding of deep sub-micron ...
CPU Design Timing Engineer
$147K - $272K/yr
Description As the CPU Design Timing Engineer, you will be responsible for the timing closure of ... synthesis, PnR, parasitic extraction, and logic equivalence Understanding of deep sub-micron ...
CPU RTL Design Engineer
Hillsboro, OR · On-site
Life at Intel The Role and Impact As a CPU Logic Design Engineer, you will play a central role in shaping Intel's next-generation processors. You will focus on designing and optimizing the logic for ...
CPU RTL Design Engineer
Hillsboro, OR · On-site
Life at Intel The Role and Impact As a CPU Logic Design Engineer, you will play a central role in shaping Intel's next-generation processors. You will focus on designing and optimizing the logic for ...
Cpu Synthesis Design Engineer information
See salary details
$40.5K - $51.2K
2% of jobs
$51.2K - $62K
11% of jobs
$67.7K is the 25th percentile. Wages below this are outliers.
$62K - $72.7K
23% of jobs
The median wage is $79.6K / yr.
$72.7K - $83.4K
22% of jobs
$83.4K - $94.1K
17% of jobs
$94.4K is the 75th percentile. Wages above this are outliers.
$94.1K - $104.9K
9% of jobs
$104.9K - $115.6K
6% of jobs
$115.6K - $126.3K
3% of jobs
$126.3K - $137K
3% of jobs
$137K - $147.8K
2% of jobs
$147.8K - $158.5K
1% of jobs
$40.5K
$88.2K
$158.5K
How much do cpu synthesis design engineer jobs pay per year?
As of Jun 9, 2026, the average yearly pay for cpu synthesis design engineer in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.
What are the main challenges a CPU Synthesis Design Engineer faces when transitioning from RTL to gate-level implementation?
One of the primary challenges for CPU Synthesis Design Engineers during the transition from RTL to gate-level implementation is balancing timing, area, and power constraints while ensuring functional correctness. This process often involves iterative synthesis runs and close collaboration with both RTL designers and physical design teams to resolve timing violations and meet performance targets. Additionally, engineers must be adept at analyzing synthesis reports and debugging issues related to logic optimization or tool constraints, which requires a strong understanding of both the CPU architecture and EDA tool flows.
What is the difference between Cpu Synthesis Design Engineer vs Cpu Verification Engineer?
| Aspect | Cpu Synthesis Design Engineer | Cpu Verification Engineer |
|---|---|---|
| Primary Focus | Designing and optimizing hardware logic for CPU synthesis | Verifying CPU functionality and performance through testing |
| Required Skills | Hardware description languages, synthesis tools, digital design | Hardware description languages, verification methodologies, simulation tools |
| Work Environment | Design teams, hardware development labs | Testing labs, simulation environments |
| Industry Usage | Semiconductor companies, CPU design firms | Semiconductor companies, CPU manufacturers |
The Cpu Synthesis Design Engineer focuses on creating and optimizing hardware logic for CPU synthesis, while the Cpu Verification Engineer concentrates on testing and verifying CPU functionality. Both roles require knowledge of hardware description languages and are essential in CPU development, but they serve different stages in the design process.
What are CPU Synthesis Design Engineers?
CPU Synthesis Design Engineers are specialized hardware engineers who transform digital CPU designs described in hardware description languages (HDL) into gate-level representations that can be manufactured as integrated circuits. They work on optimizing the CPU design for performance, power, and area, ensuring the design meets specification and is ready for fabrication. Their responsibilities often include logic synthesis, timing analysis, and collaborating closely with architecture and verification teams.
What are the key skills and qualifications needed to thrive as a CPU Synthesis Design Engineer, and why are they important?
To thrive as a CPU Synthesis Design Engineer, you need a strong background in digital design, hardware description languages (such as Verilog or VHDL), and computer architecture, usually supported by a degree in electrical or computer engineering. Familiarity with industry-standard EDA tools for synthesis (like Synopsys Design Compiler or Cadence Genus), timing analysis, and scripting languages (such as TCL or Python) is essential. Strong problem-solving abilities, attention to detail, and effective teamwork skills help you excel in cross-functional engineering environments. These skills ensure efficient and reliable CPU designs that meet performance, power, and area requirements in competitive semiconductor markets.
$100K - $500K/yr
Other
Posted 17 days ago
Job description
We are looking for a talented engineer to join our CPU design team to define and implement RTL for high-performance CPUs. You'll work on a CPU based on RISC-V ISA, collaborating with DV, PD, and performance teams to deliver a functional, timing, and power-converged design.
This role is hybrid, based out of Austin, TX or Santa Clara, CA.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- Experienced in CPU microarchitecture with expertise in Rename, Scheduler, ROB, Load Store, Branch Prediction, Cache or Datapath.
- Skilled in RTL coding (Verilog/VHDL) and familiar with industry-standard tools for simulation, synthesis, and power analysis.
- Proficient in debugging RTL/logic across multiple design hierarchies and pre/post-silicon environments.
- Background in microarchitecture definition, design specification, and performance-driven trade-off analysis.
What We Need
- Own RTL design and microarchitecture development for a portion of a CPU block of a high-performance RISC-V CPU.
- Collaborate closely with DV, PD, and performance engineers to meet functional, timing, and power goals.
- Use innovative techniques to optimize power, performance, and area while driving RTL experiments and evaluating results.
- Partner with validation and test teams to ensure robust pre-silicon and post-silicon execution.
- Enhance RTL design environment, tools, and methodologies to improve development efficiency.
What You Will Learn
- End-to-end exposure to CPU design from microarchitecture through timing and power convergence.
- Hands-on experience optimizing high performance CPU designs in both pre-silicon and post-silicon phases.
- Integration of open-source and industry-standard tools to improve RTL flows and results.
- Work in a deeply technical, highly collaborative team solving cutting-edge CPU design challenges.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.